The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1A, a FinFET device 10 is shown to include a source region 14 and a drain region 18 arranged on one or more underlying layers 12. Source contact 20 extends in a vertical direction from the source region 14 to a source contact 22 arranged in a horizontal plane above the source region 14. Drain contact 28 extends in a vertical direction from the drain region 18 to a drain contact 30 arranged in a horizontal plane above the drain region 18. Gate regions 34 and 38 are arranged between the source region 14 and the drain region 18. A plurality of fins 40 extends transverse to the gate regions 38 between the source region 14 and the drain region 18.
Referring now to FIG. 1B, parasitic capacitance of the FinFET device 10 limits AC performance. Some of the parasitic capacitances are illustrated in FIG. 1B. A first parasitic capacitance C1 occurs between the source contact 22 and the drain contact 30. A second parasitic capacitance C2 occurs between the source/drain contacts 20, 22, 28 and 30 and gate region 38. A third parasitic capacitance C3 occurs between the gate regions 34 and 38 and the source/drain regions 14 and 18. A fourth parasitic capacitance C4 occurs between the source contact 20 and the drain region 18.
Spacer materials having a relatively low dielectric constant (k) have been proposed to reduce parasitic capacitance. For example, a silicon nitride (SiN) spacer with a dielectric constant k˜7.5 has been used. Although other spacer materials have been proposed with lower dielectric constants (k˜5 or less), the improvement is incremental.